Home on Tianchu's Page

About Me

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Hello, I’m Tianchu Ji (冀天初), a computer engineer focusing on computer architecture for AI workload.

Being a kernel developer at Annapurna Labs, Amazon, I currently focus on performance evaluation and optimization for AI accelerators.

I received my doctorate degreen in Computer Engineering from the Stony Brook University in 2026. During my Ph.D. studying, I had been focusing on exploring the sparsity of the Multihead-Attention-based Deep Learning models and building high efficient SpMM hardware to accelerate the computation on GEMM-optimized hardware. I had also been working on hardware accelerators for LSTM models, and had helped build Medusa (our Scalable memory interconnect for many-port DNN accelerators) and a High Resolution Time-to-Digital Converter on FPGA.

I live in Sunnyvale, CA with my cat, Avery. When I’m free, I write blogs and short stories in Chinese here.

Avery

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Avery is a domestic shorthair feline with gray fur. Following illustrations show some of her daily activities.


Fig. 1 Avery making a standard cat ball pose	Fig. 2 Avery watching snow falls

Fig. 3 Avery lying against the PC case, enjoying the heat emitted by the CPU.	Fig. 4 Avery gazing over a cardboard cat house at something unknown

Curriculum Vitae

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Education #

B.Eng. in Huazhong University of Science and Technology, 2012-2016
Ph.D in Stony Brook University, 2016-2026

Work experience #

SDE, Annapurna Labs, Amazon, 2026-present
SDE Intern, Amazon Web Services (AWS), Summer 2020

Projects #

Exploring sparsity and SpMM hardware for Multi-Head Attention, 2020-2026
Long Short-Term Memory Neural Network Acceleration on FPGA, 2018-2020
High resolution Time-to-Digital Converter on FPGA, 2019-2020
Deep Learning on Spectrum Sensing and its FPGA applications, 2018-2019
Scalable memory interconnect for many-port DNN accelerators on FPGA, 2017-2018

Skills #

Programming Languages:

Programming: C/C++, Python
HDL and high-level HDL: Verilog/SystemVerilog, SpinalHDL
Deep Learning Framework and Libraries: PyTorch, Huggingface

FPGAs:

Xilinx FPGA: Spartan-6, Virtex-7 and Virtex-Ultrascale+
Altera FPGA: Stratix 10 NX

Publications #

See Publications.

Teaching #

Teaching Assistant:

ESE 345: Computer Architecture, Fall 2017
ESE 382: Digital Design using VHDL&PLDs, Spring 2018
ESE 118: Digital Logic Design, Spring 2020

Publications

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Journal and conference papers #

T. Ji, N. Balasubramanian, M. Ferdman and P. Milder, “Enabling Efficient SpMM for Sparse Attention on GEMM-Optimized Hardware with Block Aggregation”, FPGA'26 [Github]
M. Treviso et al., “Efficient Methods for Natural Language Processing: A Survey”, TACL 2023 [arXiv ver.]
T. Ji, S. Jain, M. Ferdman, P. Milder, H. A. Schwartz, and N. Balasubramanian, “On the Distribution and Sparsity of Attention within Transformers”, Findings of ACL'21 [arXiv ver.][Github]
Y. Shen, T. Ji, M. Ferdman, and P. Milder, “Argus: An End-to-End Framework for Accelerating CNNs on FPGAs”, IEEE Micro
Y. Shen, T. Ji, M. Ferdman, and P. Milder, “Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces”, in FPL'18 [arXiv ver.]

Thesis #

T. Ji, “Accelerating Sparse Attention for Large Language Models on GEMM-Optimized Hardware”, Ph.D. Thesis, Stony Brook University, 2026